Phase 1:  The basic idea here is to use a 20MHz ADC (analog to digital converter) and a 2048 byte FIFO (first in first out) memory chip .  For the ADC, I used the HI1175 that I got as a free sample from Intersil (http://www.intersil.com).  For the FIFO, I used the IDT7203, also as a free sample from IDT (http://www.idt.com).  Both of these chips come in Plastic DIP versions so that using them on a protoboard is easy. 

                    Basic Idea:          input signal -> ADC -> FIFO -> ParallelPort -> Computer

I got the original idea for this off the web a few years ago from this site:  http://www.ucl.ac.uk/~ucapwas/scope20m.html.  My "phase 1" design is very similiar to this.  I've added a buffer between the FIFO and the parallel port and the ability to generate a clock via the parallel port or an external clock chip.  I'm also using different chips.

I have made a simple oscilloscope from "free" or inexpensive chips.  The oscope uses a computer to display the waveforms and is connected via the parallel port.  So far, I have only made it a little past my "Phase 1" objective, which is a "Proof of Principle" demonstration.  The Phase 2 objective is a functioning dual-channel oscilloscope with input amplifier, timebase and trigger circuitry.  The Phase 3 objective is to put all that on a custom circuit board in a small box and demonstrate 20MHz operation.

Pictures:  Enough talk...  Here's my circuit diagram, protoboard layout, photos, and VBDOS source code for the Phase 1 design:

 
 

Circuit Diagram:    schematic_phase1d.gif (25724 bytes)  (click on thumbnail for larger image)

 
Click here for the PDF version  Click here for the original Pspice version (you will have to go to www.orcad.com and download the student version of Pspice and you will need this symbol library file that I made)

  

Layout:  layout_phase1e.gif (47722 bytes)  (click on thumbnail for larger image)

<Click here for the PDF version
 Click here for the original Pspice version (you will have to go to www.orcad.com and download the student version of Pspice and you will need this symbol library file that I made)

  

Photo of working board:  DSC00009.JPG (612179 bytes)  (click on thumbnail for larger image) 

You may notice that I've added four 390 Ohm resistors and LED's...  These are to view some of the control signals.

 

  

Notes:

Click here for my VBDOS source code.  If you don't know what VBDOS is, it is an old DOS based version of Visual Basic.  It is easy to access the parallel port with this program.  You can also use C to do the same thing.  From windows, things are a little more complicated...  If you don't know what DOS or C or Visual Basic are, you can still open the file with a text editor and see what I was doing...
 Pull-up resistor, 330p caps, and/or ferrite beads may be required on the "read" control signal out of the parallel port to prevent spontaneous FIFO reads. 

After some experimenting and investigation, I've found that the HCT version of the logic chips (7400 and 7404) are the best.  These are fast enough to work at 20MHz and can work with both CMOS and TTL levels.

    I've gotten a lot of chips for free (beside the ADC and FIFO used here) and you can too.  Many chipmakers let you request samples right off the web... 

  The Phase 2 plan is to add a timebase using a 20MHz clock chip and a ripple counter (I've done this already, but I want to make it selectable via the parallel port), a second input channel (I'll use some logic so that the one FIFO alternately gets a data point from each of the two ADC's), an input amplifier (hopefully just one opamp, will need -5VDC? via a voltage inverter? in order to see signals that drop below 0V, tricky to get it to work at 20MHz?), and a trigger circuit (maybe just a comparator and some logic?).  Want to add a register to control as much of this as possible from the parallel port (this will probably require a bi-directional parallel port [standard]).

You will need a bi-directional parallel port, because we want to input data. This may require changing the settings in CMOS setup from ECP/EPP to bi-directional.